Intel has announced new details of its upcoming consumer CPU and GPU product lines, as well as 3D Xpoint memory, the 10nm manufacturing process node, future chip packaging technology, software, and much more, in its virtual Architecture Day 2020 seminar. Senior engineers including Raja Koduri, who is a company Senior Vice President, Chief Architect, and GM of Architecture, Graphics and Software, talked about Intel’s progress on the product design as well as manufacturing fronts, offering up information about how Intel intends to be competitive now and in the future.
Starting with the 11th Gen ‘Tiger Lake‘ CPUs, which are expected to be announced as early as the first week of September, Intel disclosed that a combination of microarchitectural and manufacturing process improvements will allow for a much wider range of frequencies than the current 10th Gen ‘Ice Lake‘ processor series. This should allow CPU cores to scale up or down farther than before to accommodate power saving and performance goals.
Tiger Lake uses the ‘Willow Cove’ CPU microarchitecture. Intel’s new in-house Xe-LP integrated GPU with up to 96 execution units will also debut with this product line. Tiger Lake CPUs also feature a new cache structure and security measures aimed at mitigating control flow attacks, plus AI acceleration as well as integrated Thunderbolt 4 and USB 4. PCIe 4.0 and DDR5 RAM support will make the platform future-ready.
Intel is touting “more than a generational increase” in performance for this generation, which should allow it to make up for some of the time lost due to repeated delays with 10nm production over the past several years. PCs built using Tiger Lake CPUs are expected to go on sale in late 2020. No further announcements were made about the delayed transition to 7nm following this.
The company has dropped its confusing “+” suffixes and will instead use the term “10nm SuperFin” to brand the latest improvement of its 10nm process. Intel is calling this the largest intra-node enhancement in its history, as it has improved the structure of its FinFET transistors to improve performance and power efficiency without a generational drop in fabrication size. SuperFin transistors are said to allow better passage of current with improved interconnects, lower resistance, and reduced voltage droop.
The SuperFin transistors’ improvements have been achieved using a “super lattice” structure of High-K dielectric materials in a stack measuring a few angstroms thick. Intel says that this is an industry-leading development that is ahead of its competitors’ capabilities, and is already in use with Tiger Lake chips.
While the Xe-LP (low power) integrated GPU will begin rolling out in 2020, Intel also detailed plans for Xe to scale up to discrete graphics cards, enthusiast gaming PCs, and server as well as data centre applications. Xe-LP is only one implementation, and is optimised for size and power. It features up to 96 execution units and will support asynchronous compute, AI inferencing, an updated media encode/decode engine, 12-bit colour, four display pipelines, variable rate shading, adaptive sharpening, and adaptive sync with variable refresh rates up to 360Hz.
Performance in games for Xe-LP in a 15W package is said to match or exceed what Intel’s current Gen11 integrated GPU can achieve in a 25W envelope. Intel says users can expect to run games at high settings with better frame rates than current integrated GPUs can manage at low settings.
For PC gamers, Intel announced a new Xe-HPG implementation of its high-power Xe-HP GPU, coming in 2021. The only details confirmed so far are that it will support hardware ray tracing and use GDDR6 memory. Interestingly, this GPU will be manufactured using a third-party foundry and leveraging external process technology, which Intel recently indicated it would start doing to improve its ability to get products to market.
The high-end Xe-HP variant is designed to be scalable to power high-end media encoding and streaming as well as AI acceleration capabilities in the datacentre. It was demonstrated transcoding 10 4K 60fps video streams simultaneously on one modular logic block, and up to four of these blocks can be implemented on a GPU.
In other announcements, Intel confirmed that Alder Lake will be its next hybrid CPU design, following Lakefield. It will combine next-gen Golden Cove and Gracemont cores for flexibility, power and efficiency. No further details including a launch timeframe have been announced, but it is widely expected that Alder Lake will form the basis of the 12th Gen lineup for desktops and laptops.
For servers and datacentres, Intel will ship its next-gen Xeon Scalable CPUs based on the Ice Lake-SP architecture later this year, supporting total memory encryption and PCIe 4.0. Following that, the Sapphire Rapids generation will leverage 10nm SuperFin transistors and will support PCIe 5.0 with DDR5 memory.
Intel also presented updates on its FPGA product lines, 3D Xpoint persistent memory, 144-layer 3D NAND flash, Loihi neuromorphic processing research, next-gen Foveros and EMIB packaging technology, OneAPI programming model, and DevCloud developer tools.